Verification Engineer

A leading global company is looking for verification engineer!;   

• Responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.• Create a constrained-random verification environment using SystemVerilog.• Identify and write all types of coverage measures for stimulus and corner-cases.• Debug tests with design engineers to deliver functionally correct design blocks.• Collaborate closely with design and verification engineers in active projects and perform hands-on verification. • Close coverage measures to identify verification holes and to show progress towards tape-out.