Job Description

Description:

  • We are looking for a talented Design Verification Engineer.



    • Job Responsibilities:

  • Plan & implement UVM verification environments developing tests, testbenches, UVM components, and regressions/test lists
  • Responsible for generating and executing the Verification Test Plan and Verification Requirement Matrix
  • Interact with Architecture, Design, SW and Validation teams
  • Define new DV methodologies and improve existing ones
  • Work on both ASIC and FPGA Space system projects



    • Job Qualifications:

  • 7+ years of relevant design verification experience
  • Proficiency in FPGA/ASIC Verification development methodology
  • Proficiency in System Verilog and UVM
  • Knowledge and experience with FPGA tools (Vivado/Quartus/VCS).



    • Preferred Job Qualifications:

  • Experience validating complex SOC designs
  • Experience valida...

    • Ready to Apply?

    Take the next step in your AI career. Submit your application to Protingent today.

    Submit Application