Job Description
TPU RTL Design Engineer, Networking, Inter-Chip Interconnects
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 4 years of experience in high-performance ASIC design.
+ Experience architecting or designing RTL solutions for digital systems.
+ Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers.
+ Experience with high-speed interconnects.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 4 years of experience in high-performance ASIC design.
+ Experience architecting or designing RTL solutions for digital systems.
+ Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers.
+ Experience with high-speed interconnects.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
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