Timing Optimization Engineer

Job Title: Synthesis Engineer

Experience: 3+ Years

Domain: VLSI / ASIC Design

Job Summary:

We are looking for a skilled Synthesis Engineer with 3+ years of experience in RTL-to-Gate synthesis and timing optimization. The candidate will be responsible for achieving timing, area, and power targets while ensuring high-quality netlist generation for downstream Physical Design.

Key Responsibilities:

• Perform RTL-to-Gate synthesis and netlist generation
• Apply and validate SDC timing constraints
• Drive timing, area, and power optimization
• Work on multi-mode multi-corner (MMMC/MCMM) synthesis flows
• Analyze and fix synthesis-related timing violations
• Collaborate with RTL, DFT, and Physical Design teams
• Support