Job Description

  • Technical Lead for Virtual Prototype and System Modelling using SystemC/TLM2.0/CCI/UVM and industry standard ESL tools (e.g Synopsys Virtualizer, ASTC, VLAB etc.)
  • Responsible for Requirements analysis, System C model architecture and high-level/low-level designs.
  • Owns the implementation of SystemC Models and its unit level verification.
  • Responsible for VP Integration, System Testing and debugging, usingin-house verification platforms. E.g. Co-verification platforms consisting of Low-level device drivers and startup SW, RTL SoC verification environment etc.
  • Responsible for quality audits and VP delivery to both external(OEM, Tier-1 and SW eco-system partners) and internal stakeholders ( SW development, application engineering teams)
  • Debug and resolve all technical issues from the external and internal stakeholders in a timely manner and support with new use cases.
  • Identify and mitigate all the technical risk in area of responsibili...

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