Technical Lead Design Verification Engineer

Job Description

We are looking for aTechnical Lead Design Verification Engineer with proven experience in all aspects of verification in UVM and C/C . The candidate must have experience using high level programming languages such as C/C to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is
  required, and a Maser's is preferred.
• ≥5 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast wi...