Job Description


Job Description:

  • The Verification Engineer will contribute to the pre-silicon functional verification of high-performance SoCs and related subsystems.

  • This role requires a senior-level verification engineer who can work independently and take ownership of verification deliverables within a UVM/SystemVerilog environment.

  • The engineer will collaborate with design, architecture, and validation teams to ensure thorough functional and coverage verification prior to tape-out.

    • Responsibilities:


  • Perform pre-silicon functional verification of digital designs using UVM and SystemVerilog methodologies.

  • Develop, enhance, and maintain UVM-based testbenches, sequences, and scoreboards for block and system-level verification.

  • Write and execute constrained-random and directed testcases; implement coverage models and assertions to ensure design quality and completeness.

  • Debug functional and si...

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