SystemVerilog Verification Expert

Senior Design Verification Engineer

Location: Bangalore.

Experience: 4 to 10 Years.

Notice Period: Any.

• Perform verification of complex digital designs at block and system level.
• Develop testbenches using SystemVerilog/UVM for simulation and debugging.
• Create and execute comprehensive test plans for functional verification.
• Achieve coverage targets using code and functional coverage metrics.
• Work closely with RTL design and architecture teams to identify issues.
• Debug simulation failures and trace root causes effectively.
• Run regressions and maintain automated verification flows.
• Familiarity with formal verification and assertion-based techniques.
• Proficient in tools like VCS, Questa, Verdi, and waveform viewers.
• Experience with scripting languages like Python, Perl, or Tcl.
• S...