SystemVerilog UVM Verification Engineer

Job Description:

We are looking for Design Verification Engineers with strong expertise in IP / SoC / Low-Power Verification

- Solid experience in Design Verification using SystemVerilog & UVM.

- Hands-on Testbench development experience (scoreboard, drivers, sequencers, checkers, agents)

- Experience in IP-level or SoC/Sub-system level verification.

- Good understanding of protocol-based verification (AXI, PCIe, CHI, UCIe, etc.)

- Exposure to Low-Power verification / UPF / power-aware simulations is a plus.

- Strong debugging, coverage analysis, and problem-solving skills.

Thanks,

Karthik Kumar

[email protected]