Job Description
Location is San Jose, CA - Hybrid Work Environment (As of now), 3 days in Office (Tue, Wed, Thu)
Interview: MS Teams
We are looking for someone with close to 3-5 years of experience in hardware design.
Must have skills:
- FPGA Design Experience
- RTL Design using Verilog/System Verilog
- Exposure to any Emulation or Prototyping Platform (HAPS/Zebu, Protium/Palladium)
JOB DUTIES:
In this position, the engineer will have the following key responsibilities: Hardware emulation model creation. Importing design RTL. Provide RTL patches to address non-synthesis issues. Compile emulation model. Debugging issues found during the process, bring-up, validation, and production phases of SOC programs. Perform pre-silicon verification & validation and emulation to ensure functional correctness and performance. Partition large SoC RTL for multi FPGA platforms; develop and maintain HAPS/FPG...
Interview: MS Teams
We are looking for someone with close to 3-5 years of experience in hardware design.
Must have skills:
- FPGA Design Experience
- RTL Design using Verilog/System Verilog
- Exposure to any Emulation or Prototyping Platform (HAPS/Zebu, Protium/Palladium)
JOB DUTIES:
In this position, the engineer will have the following key responsibilities: Hardware emulation model creation. Importing design RTL. Provide RTL patches to address non-synthesis issues. Compile emulation model. Debugging issues found during the process, bring-up, validation, and production phases of SOC programs. Perform pre-silicon verification & validation and emulation to ensure functional correctness and performance. Partition large SoC RTL for multi FPGA platforms; develop and maintain HAPS/FPG...
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