Standard Cell Layout Design Engineer (Tijuana)

Company & Job Area
QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA – Engineering Group, ASICS Engineering
Job Summary
Design and develop physical layouts for logic standard cells using industry-standard computer-aided design (CAD) tools, such as Cadence Virtuoso.
This role involves leveraging scripting and algorithmic programming languages, including SKILL and Python, to support layout automation, optimization, and design efficiency.
Responsibilities
Perform comprehensive layout verification, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC).
Collaborate closely with circuit designers to ensure layouts meet quality, performance, and reliability requirements.
Maintain and manage layout databases using designated Design Management software.
Engage with the engineering design team to understand design concepts, constraints, and project milestones; accurately and concisely communicate ...