Staff IP Design Engineer

Responsibilities & Skills

We are seeking a Staff IP Design engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The individual should have the ability to work closely with architect to translate specifications into high-speed RTL design, for the best Performance, Power and logic utilization.

Requirements Key Skills

• Experience in high speed SERDES and video protocols (e.g.: DisplayPort, HDMI, MIPI, SDI) or Peripherals (SPI, I2C or I3C) is a plus.
• Hands‑on experience in FPGA RTL design, logic verification, debug and timing closure is preferred.
• Programming skills (e.g.: C/C++, Perl, TCL or Python).
• Experience in hardware validation or hardware interoperability test is a plus.
• Experience in soft IP packaging, example design and testbench development will be an added advantage.

Education And General

• BS/MS/PhD...