Staff Engineer Functional Verification

As a Staff Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.

The Role

· Reading and analysing the system requirements and architecture requirement documents.

· Developing detailed Test and Coverage plans based on the Architecture and Micro-architecture.

· Developing Verification Methodology, ensuring scalability and portability across environments.

· Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.

· Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug o...