Staff DFT Design Engineer

Key Responsibilities

• Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms
• Drive DFT requirements at architecture and RTL definition stages, influencing design trade‑offs early
• Own DFT methodology evolution, including scalability, reuse, and long‑term roadmap alignment
• Lead design reviews and collaborate with stakeholders to drive closure

Advanced DFT Implementation & Sign-Off

• Provide hands‑on leadership for complex DFT implementations, including but not limited to Scan Architecture, Scan Insertion, ATPG pattern generation and coverage analysis, Cell‑Aware, Power‑Aware, Memory BIST and Repair, Streaming Scan Network (SSN), ICL extraction & PDL retargeting, etc.
• Strong knowledge on industrial test standards IEEE 1149.1 (JTAG) and/or IEEE 1687 (IJTAG)
• Drive DFT sign‑off quality using tools such as SpyGlassDFT or equivalent
• Resolve complex testability, clo...