Job Description
Become a Staff ASIC Design Verification Engineer at Synopsys, focusing on the dynamic field of High-Bandwidth Memory products. Utilize your System Verilog proficiency in driving technological advancements.
At Synopsys, you will work within a skilled team dedicated to the next generation of mixed-signal designs. Your role involves verifying ASIC RTL designs across various levels. The position calls for proactive problem-solving and effective collaboration with internal and external stakeholders to ensure high standard outcomes.
Key Responsibilities:
• Conduct verification of ASIC RTL designs
• Develop and maintain comprehensive verification test plans
• Write and design System Verilog testbenches using UVM
• Perform Functional Coverage analysis and Assertions
• Debug and troubleshoot simulation and firmware failures
Requirements:
• BSEE or MSEE with a minimum of 2 years' related experience
• In-depth knowledge of System Verilog and UVM
• Capable of debug...
At Synopsys, you will work within a skilled team dedicated to the next generation of mixed-signal designs. Your role involves verifying ASIC RTL designs across various levels. The position calls for proactive problem-solving and effective collaboration with internal and external stakeholders to ensure high standard outcomes.
Key Responsibilities:
• Conduct verification of ASIC RTL designs
• Develop and maintain comprehensive verification test plans
• Write and design System Verilog testbenches using UVM
• Perform Functional Coverage analysis and Assertions
• Debug and troubleshoot simulation and firmware failures
Requirements:
• BSEE or MSEE with a minimum of 2 years' related experience
• In-depth knowledge of System Verilog and UVM
• Capable of debug...
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