STA Design Engineers

JD

STA, Timing Closure is must

We are looking for profiles, with some PD experience, like Placement and Routing (PnR), Static Timing Analysis (STA) along with TCL scripting with 1+ years of experience along with FPGA Design.

• BS or MS in EE or CE with 2+ years of experience in digital design and/or timing closure.

• Strong background in RTL design using Verilog/VHDL.

• Timing Constraints (SDC) & Static Timing Analysis .

• Strong understanding and usage of ASIC and/or FPGA software tool

chain like Vivado or Quartus.

• Strong Digital Design Fundamentals and applications

• TCL Scripting language

• • Applications and Designs in Wireless/Wired domain.