Job Description
Sr Staff Engineer, Synthesis and STA
Job Description
We are seeking a seasoned **Backend Design Expert specializing in Static Timing Analysis (STA)** and **Logic Synthesis** . You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.
**Key Responsibilities**
+ Physical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization). Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets. Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist. UPF management for multi...
Job Description
We are seeking a seasoned **Backend Design Expert specializing in Static Timing Analysis (STA)** and **Logic Synthesis** . You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.
**Key Responsibilities**
+ Physical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization). Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets. Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist. UPF management for multi...
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