Job Description


Job Description

We’re looking for a Senior Engineer (5+ Years) in design enablement space, with strong RTL and static verification expertise to help build robust design-quality methodologies across our teams.

Key Skills

  • Strong RTL design experience (Verilog/SystemVerilog)
  • Strong hands-on knowledge of Lint, CDC, RDC flows
  • Tcl and shell scripting 
  • Python (good to have)
  • Ability to debug RTL/static issues and improve design quality

    • Qualifications

    ​​​​Role

  • Develop & maintain design enablement methodologies
  • Drive Lint/CDC/RDC signoff flows
  • Automate checks and design workflows
  • Collaborate with design teams to ensure high-quality RTL
  • Create guidelines and best practices
  • If you’re passionate about methodology, automation, and enabling high-quality RTL design teams, we’d love to connect!

    • Company Description

    Renesa...

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