Job Description

Must Have skills (Technical + Behavioral)

  • Methodology: UVM
  • Languages: System Verilog
  • Verification knowledge is must. Person should have worked on UVM based design verification
  • Should have expertise in either IP level DV or SoC level DV
  • Protocol Knowledge: PCIe OR Ethernet OR DDR OR AXI/ SPI/ UART or any other protocol
  • >7Y Person should have lead a team of 5 member team for technical side of project
  • Good oral and written communication skills. This job requires the ability to work effectively within diverse teams.

Good to Have skills (Technical + Behavioral)

  • Knowledge of the Perl Scripting language
  • Intel project experience


Skills Required
Perl Scripting, Ms Office, Problem Solving, System Verilog

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