Job Description

Hi - We are looking for a senior ASIC Design Verification engineer who owns testbench architecture, not just tests. This role is about building scalable UVM environments and driving SoC verification from spec to silicon.

Experience: 8+ years (ASIC only)
Location Bangalore

What you will do

Architect and build scalable UVM testbenches from scratch at subsystem and SoC level
Own testbench architecture: structure, reuse, scalability, maintainability
Define verification strategy and test plans from specs and micro-architecture
Develop tests, scoreboards, checkers, SVA, and coverage models
Drive functional, code, and assertion coverage closure
Lead SoC-level verification: IP integration, coherency, low power, resets/boot
Debug complex issues and support pre/post-silicon correlation

What we need

8+ years of hands-on ASIC verification (FPGA/emulation-only doesn’t count)
Strong ownership of TB architecture, not just test writi...

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