SoC Synthesis Engineer: Optimize PPA for High-Perf ASIC

Qualcomm is seeking a SoC Design & Synthesis Engineer in Baja California to synthesize RTL into gate-level netlists, ensuring timing, power, and DFT readiness before PD handoff. You will work with Design, DFT, and Physical Design teams to optimize PPA and support post-change validation across Snapdragon platforms.

The role requires hands-on experience with large-scale SoC synthesis, functional ECOs, and debugging under tight schedules.