Job Description

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
  • 5 years of experience in ASIC physical design flows with emphasis on physical verification convergence and tapeout signoff.
  • Experience in ASIC physical design, physical design verification, and various methodologies.
  • Experience in physical verification tools, Python, Tcl, or Perl scripting.

Preferred qualifications:

  • Master's degree in Electrical Engineering, or a related field.
  • Experience in Padrings, Bumps, Redistribution Layer (RDL), and IP integration (e.g., memories, IOs, and analog IPs).
  • Experience in Place and Route (PnR) tools like Fusion Compiler or Innovus with physical convergence.
  • Knowledge of semiconductor device physics and translator characteristics.

About The Job

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