Job Description

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 4 years of experience with physical design.
  • Experience in block level synthesis, floor-planning, place and route, clock tree synthesis (CTS), timing closure and power analysis.
  • Experience with System on a Chip (SoC) cycles.

Preferred qualifications:

  • Master's degree in Electrical Engineering.
  • Experience in coding with System Verilog and scripting with TCL.
  • Experience with layout verification and design rules.
  • Experience in VLSI design in SoC.
  • Experience in using physical design tools like Place and Route tools (P&R), Static Timing Analysis (STA) tools, and physical verification tools.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future ...

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