Job Description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in ASIC design verification methodology.
- Experience in leading or managing IP or SS verification teams.
- Experience in UVM based IP and SS/SOC verification.
- Experience with programming in Verilog, SystemVerilog, and Perl/Python.
- Experience with industry-standard EDA tools and methodologies.
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 15 years of experience in ASIC design verification methodology.
- Experience in Portable Test and Stimulus Standard (PSS) , Formal or emulation based Simulation Accelerator (SimXL) methodologies.
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