Senior/Staff Design Verification Engineer (SOC)

We are seeking a talented Design Verification Engineer to join our IC development team and help ensure the functional correctness and robustness of complex digital designs. In this role, you will work closely with design and verification teams to develop comprehensive verification environments, execute test plans, and contribute to high‑quality silicon through systematic and coverage‑driven verification.

• Apply UVM (Universal Verification Methodology), SystemVerilog, Verilog, and SVA (SystemVerilog Assertions) languages in verification tasks.
• Develop and implement state‑of‑the‑art verification methodologies, including UVM, C/C++, co‑simulation, system emulation, and mixed‑mode simulation/emulation.
• Contribute to projects requiring advanced verification tools such as Palladium, HAPS, and Zebu platforms.
• Collaborate effectively within a team, ensuring high‑quality deliverables.