Senior System-on-Chip (SoC) Verification Engineer

HI All,

I am currently looking for Senior Design Verification ( ASIC - SOC) Engineers for BLR & HYD Location.

Exp - 10+ yrs

Location - BLR & HYD

Notice Period - Immediate to 15 days

Client - Product client.

JD:

10+ yrs of experience for the leads, 5+ for others.

- Strong experience in SV and UVM.

- Scripting languages - such as Python/ Perl

- Industry standard tools like vcs, Verdi, etc.

- Experience in creating and maintaining testbenches in SV / UVM

- Experience with networking SoCs good to have.

- High speed Serdes experience

- Functional coverage and assertions - Ensure coverage goals are met

- GLS - zero delay & SDF.

- X prop simulations.

Interested candidates, Kindly share with me your updated profile to [email protected] OR Call me +9...