Senior Principal SOC RTL Architect | VLSI & Low-Power

MaxLinear, Inc. seeks a Senior Principal SOC Design Engineer to lead pre-silicon RTL coding for block, IP, and top-level SOC integration. You will develop reusable RTL code with a modular approach, and drive verification and timing/low-power strategies across cross-functional teams.

Deep expertise in VHDL/Verilog, NoC interconnect, and ARM ecosystem is required, along with strong debugging and automation skills to elevate pre-silicon readiness and IP integration.