Senior PCIe Verification Engineer (SV/UVM)

UST Malaysia in Bayan Lepas, Penang, Malaysia seeks an experienced verification engineer to verify PCIe IP/SoC designs. You will build reusable SystemVerilog/UVM environments, develop directed and constrained-random test cases, and ensure coverage goals are met across Gen3/Gen4/Gen5 PCIe protocols.

Responsibilities include debugging RTL, waveform analysis, and supporting verification closure, while collaborating with design and validation teams to drive sign-off and regression testing.