Job Description

Highly autonomous engineer with 5–8 years of experience spanning unit-cell to complex chip-level layout implementation and physical verification.


This role balances rigorous technical execution, client management, deep DRM knowledge, and workflow innovation (BKMs) with active team leadership—overseeing task delegation, driving post-mortems, mentoring talent, and maintaining high-value client relationships to ensure on-time, high-quality delivery.

  •   Technical Execution & Verification Sign-Off Unsupervised Layout Implementation: Independently execute layout designs across all hierarchies—from unit cells and blocks to complex MACRO, PHY, and full-CHIP levels—without supervision.


    Autonomous Physical Verification: Own the complete verification flow (DRC, LVS, etc.).


    Ensure all results are double-checked, remaining errors are formally waived/confirmed, and comprehensive documentation is provided.


    Architectura...

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