Senior Digital Logic Design Engineer

Job Responsibilities:

• Designkey digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs
• Develop strong understanding of heterogenous processor cores & subsystems (A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements
• Package Digital IP for seamless integration into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc
• Consolidate & curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces & peripherals
• Evaluate 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testabilit...