Job Description
Senior DFT Static Timing Analysis Engineer, Google Cloud
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 5 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).
+ Experience in DFT architectures and associated test methodologies.
+ Experience in Tessent generated DFT timing constraints, SSN bus networks and constraints and mode merging.
+ Experience with EDA tools and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk....
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 5 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).
+ Experience in DFT architectures and associated test methodologies.
+ Experience in Tessent generated DFT timing constraints, SSN bus networks and constraints and mode merging.
+ Experience with EDA tools and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk....
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