Senior DFT Design Engineer

DFT Architecture & Implementation

• Define, implement, and maintain DFT strategies for FPGA designs to meet quality, coverage, and manufacturability goals.
• Hands‑on implementation and debug of DFT features including Scan Architecture, Scan Insertion, ATPG pattern generation and coverage analysis, Cell‑Aware, Power Aware, Memory BIST and Repair, Streaming Scan Network (SSN), ICL extraction & PDL retargeting
• Strong knowledge on industrial test standards IEEE 1149.1 (JTAG) and/or IEEE 1687 (IJTAG)
• Drive DFT sign‑off using industry tools including review RTL, Netlist & Test Plan for DFT compliance & testability risks
• Support post‑silicon power‑on, test content debug & coverage optimization

Timing & Physical Design Collaboration

• Develop and validate timing constraints for DFT logic
• Work closely with Front End IP Design & Physical Design teams to meet timing closure for DFT paths
• R...