Senior Design Verification Engineer - RTL/UVM Expert

Lattice Semiconductor is seeking a Design Verification Engineer to join their R&D organization in George Town, Malaysia. This role offers the opportunity to develop and review test plans, create complex verification environments, and implement coverage metrics within a dynamic team.

The ideal candidate should possess strong understanding of the verification process, HDL skills, and expertise in programming. A minimum of 12 years in SystemVerilog/UVM is required. Lattice supports a fast-paced, collegial working environment!