Senior Design Verification Engineer

HSIO PHY Verification Engineer (SV/UVM)
Experience:

5–12 Years
Location:

Bengaluru
Company:

Tessolve Semiconductor
Job Summary
We are looking for an experienced

HSIO PHY Verification Engineer

with strong expertise in

SystemVerilog (SV)

and

UVM methodology

to join our verification team in Bengaluru. The candidate will be responsible for verifying high-speed interface PHY IPs and ensuring first-pass silicon success.
Key Responsibilities
Develop and execute verification plans for

HSIO PHY IPs

(PCIe, USB, MIPI, SATA, SerDes, etc.).
Build and enhance UVM-based verification environments from scratch.
Develop SystemVerilog testbenches, sequences, scoreboards, assertions, and coverage models.
Perform protocol-level and PHY-level verification.
Debug complex issues at RTL, gate-level, and system-level simulations.
Work closely with RTL design, analog/mixed-signal...