Job Description
Job Title: Senior Design Verification Engineer – IP/So C/Processor/GLS
Experience: 5 to 30 Years
Location: (Insert Location – e.g., Bangalore / Hyderabad / Chennai / Noida / Remote)
Company: Tessolve Semiconductor
Job Type: Full-Time | Permanent
Domain: Semiconductor – Design Verification
Job Summary:
Tessolve is hiring experienced Design Verification Engineers with a strong background in IP and So C-level verification , along with specialization in one or more of the following areas: processor/microarchitecture verification , high-speed interfaces (e.g., PCIe, USB, DDR) , or GLS (Gate-Level Simulation) . This role involves ownership of verification strategy, planning, and execution in pre-silicon environments using industry-leading tools and methodologies.
Key Responsibilities: Develop and execute detailed verification plans for IP blocks, subsystems, or So Cs. Design and build System Verilog/UVM-based testbenches , scoreboards, monitors, and drivers....
Experience: 5 to 30 Years
Location: (Insert Location – e.g., Bangalore / Hyderabad / Chennai / Noida / Remote)
Company: Tessolve Semiconductor
Job Type: Full-Time | Permanent
Domain: Semiconductor – Design Verification
Job Summary:
Tessolve is hiring experienced Design Verification Engineers with a strong background in IP and So C-level verification , along with specialization in one or more of the following areas: processor/microarchitecture verification , high-speed interfaces (e.g., PCIe, USB, DDR) , or GLS (Gate-Level Simulation) . This role involves ownership of verification strategy, planning, and execution in pre-silicon environments using industry-leading tools and methodologies.
Key Responsibilities: Develop and execute detailed verification plans for IP blocks, subsystems, or So Cs. Design and build System Verilog/UVM-based testbenches , scoreboards, monitors, and drivers....
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