Job Description
Silicon Patterns seeks Design Verification Engineers with 5+ years, Location: Bangalore,
Skills: DDR
Key Responsibilities
Develop and maintain UVM-based testbenches for DDR IP and So C-level verification, including constrained-random stimulus, functional coverage, and assertions.
Debug verification failures, collaborate with design teams on protocol compliance (e.g., DDR timing, memory controllers), and ensure first-pass silicon success.
Lead or contribute to test plans, coverage closure, and emulation flows for high-performance computing projects.
Required Skills
5-10+ years in design verification with hands-on DDR expertise; proficiency in System Verilog, UVM, and protocols like PCIe, Ethernet.
Experience with verification tools (e.g., Questa, VCS), coverage-driven methodologies, and scripting (Perl/Python).
Strong problem-solving for IP/So C blocks in domains like AI/ML, automotive, or Io T.
Company Overview
Silicon Patterns is a specialized engineer...
Skills: DDR
Key Responsibilities
Develop and maintain UVM-based testbenches for DDR IP and So C-level verification, including constrained-random stimulus, functional coverage, and assertions.
Debug verification failures, collaborate with design teams on protocol compliance (e.g., DDR timing, memory controllers), and ensure first-pass silicon success.
Lead or contribute to test plans, coverage closure, and emulation flows for high-performance computing projects.
Required Skills
5-10+ years in design verification with hands-on DDR expertise; proficiency in System Verilog, UVM, and protocols like PCIe, Ethernet.
Experience with verification tools (e.g., Questa, VCS), coverage-driven methodologies, and scripting (Perl/Python).
Strong problem-solving for IP/So C blocks in domains like AI/ML, automotive, or Io T.
Company Overview
Silicon Patterns is a specialized engineer...
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