Senior Design Verification Engineer

Silicon Patterns seeks Design Verification Engineers with 5+ years,

Location: Bangalore,

Skills: DDR

Key Responsibilities

• Develop and maintain UVM-based testbenches for DDR IP and SoC-level verification, including constrained-random stimulus, functional coverage, and assertions.
• Debug verification failures, collaborate with design teams on protocol compliance (e.g., DDR timing, memory controllers), and ensure first-pass silicon success.
• Lead or contribute to test plans, coverage closure, and emulation flows for high-performance computing projects.

Required Skills

• 5-10+ years in design verification with hands-on DDR expertise; proficiency in SystemVerilog, UVM, and protocols like PCIe, Ethernet.
• Experience with verification tools (e.g., Questa, VCS), coverage-driven methodologies, and scripting (Perl/Python).
• Strong problem-solving for IP/SoC blocks in domai...