Senior Design Verification Engineer

• Develop and execute verification plans for PCIe IP/SoC designs.
• Build and maintain SystemVerilog/UVM verification environments.
• Develop directed and constrained-random test cases to achieve coverage goals.
• Verify PCIe protocol (Gen3/Gen4/Gen5), including protocol compliance and functional correctness.
• Debug RTL and simulation issues, analyze waveforms, and support verification closure.
• Develop and execute verification plans for Clock (CLK) and PLL IPs.
• Create directed and constrained-random test cases to validate functionality and performance.
• Perform functional coverage analysis, debug simulation failures, and root cause issues.
• Collaborate with design, architecture, and validation teams to ensure verification completeness.
• Support regression testing and verification sign-off.

Requirements

• Bachelor's or Master's degree in Electrical/Electronics Engineer...