Senior CAD Developer - Timing and Physical Design Optimization

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.







What You’ll Be Doing:

+ Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.

+ Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, IR drop optimization

+ As with any software engineering team, we do write a l...