Senior ASIC Verification Engineer - SystemVerilog & UVM

A leading technology design services company in Ottawa is seeking an experienced ASIC Verification Engineer with 8 to 12 years of expertise. The role involves validating architectural functional blocks and developing verification plans using System Verilog and UVM. Strong analytical and programming skills in C and Python are essential. Join a team that values innovation and collaboration while working on cutting-edge technology in an inclusive environment.
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