RTL Design Engineer (5-15 Years)

We are looking for an experienced RTL Design Engineer with strong hands-on expertise in ASIC RTL development.

This role focuses on designing high-quality RTL blocks, algorithm implementation, and design validation.

Strong experience in coding RTL blocks / algorithms using Verilog / SystemVerilog

Ability to translate micro-architecture into synthesizable RTL considering area, latency, and power

Experience running QC checks (CDC, Lint, X-prop) and resolving design issues

Exposure to synthesis and constraint development is an added advantage

If you enjoy working on complex RTL design challenges and driving robust silicon implementations, this opportunity is for you.

Regards,

Karthik Kumar