Principal Physical Design Engineer

Principal Physical Design Engineer – SoC Middle‑End (RTL2NETLIST)

Responsibilities

• Perform design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of functional constraints
• Create timing constraints for functional, DFT modes for synthesis/STA by working closely with Design and DFT Engineers
• STA/timing closure
• Write low power intent file (CPF/UPF) from specification and verify correctness of power intent file using CLP/VCLP
• Perform logic equivalence checks
• Work with physical design engineer to resolve all netlist and timing issues

Qualifications

• Master’s/Bachelor’s Degree in Electrical/Electronics Engineering with an emphasis in IC design
• Good experience with Synopsys tool suite or Cadence toolsuite
• Proficient in TCL scripting, python knowledge is a ++
• Able to work in a team with a strong drive to excel
• Able to work indep...