Job Description


Job Description

We are seeking a Principal Engineer – Implementation Lead to own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs implemented on cost-optimized mature process nodes. This role is critical for ensuring design quality and convergence while meeting power, performance, and cost targets.

Job Description

  • Drive RTL-to-gate synthesis for complex multi-die MCU designs using industry-standard tools
  • Optimize for timing, power, and area while adhering to mature-node constraints
  • Lead static timing analysis (STA) and timing closure activities across multiple corners and modes
  • Ensure sign-off compliance for timing, power, and signal integrity
  • Work closely with RTL, DFT, and physical design teams to resolve timing issues
  • Own full chip constraints and design optimizations to achieve convergence
  • Define and maintain synthesis and timing closure methodologies tailored for cost-sens...

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