Job Description

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Key Responsibilities

  • Lead end-to-end RTL-to-GDSII execution for a given SoC program, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts.
  •  Owned timing, power, and physical signoff strategy, including STA, SI, IR/EM analysis, ensuring first-pass silicon success and high design reliability.
  •  Established and enforced DRC/LVS closure methodologies, led physical verification, and streamlined ECO flows to meet aggressive tapeout schedules.
  •  Partnered with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle.
  •  Defined and deployed automated design methodologies using TCL, Python, and Perl; collaborated with CAD teams to improve flow efficiency and scalability.
  •  Championed low-power design strategies (UPF/CPF), enablin...

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