Job Description
Responsibilities:
Independently handling Block level PnR implementation with industry-standard tools.
Perform physical design tasks, including Synthesis, floorplanning, placement, routing, and optimization, to create high-performance, low-power designs that meet project requirements.
Responsible for Clock Tree Synthesis, Physical Verification (DRC and LVS), and taking blocks to closure.
Ownership of digital sub-blocks/chip level (specification and implementation).
Definition of new test cases similar to product definition and for designing significant blocks of chip, including chip architecture and chip top integration, with a focus on improving Quality of Design System.
Responsibility for the setup and running of test cases, analyzing failures, and bug fix validation and verification by analyzing all device models/components in the technology and ensuring ~100% coverage in the test plan/test cases.
Requirements
Strong understanding of the RTL2GDSII flow o...
Independently handling Block level PnR implementation with industry-standard tools.
Perform physical design tasks, including Synthesis, floorplanning, placement, routing, and optimization, to create high-performance, low-power designs that meet project requirements.
Responsible for Clock Tree Synthesis, Physical Verification (DRC and LVS), and taking blocks to closure.
Ownership of digital sub-blocks/chip level (specification and implementation).
Definition of new test cases similar to product definition and for designing significant blocks of chip, including chip architecture and chip top integration, with a focus on improving Quality of Design System.
Responsibility for the setup and running of test cases, analyzing failures, and bug fix validation and verification by analyzing all device models/components in the technology and ensuring ~100% coverage in the test plan/test cases.
Requirements
Strong understanding of the RTL2GDSII flow o...
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