Job Description

Experience

  • 3-6 years

    • Role and responsibility:

  • Ability to execute block level P&R and Timing closure activities.
  • Will be responsible for owning up block level P&R.
  • Perform Netlist2GDS on blocks
  • Implementation of multimillion gate SoC designs in cutting edge process
    technologies (28nm,16nm,14nm & below ).
  • Strong Hands-on expertise on any of the aspects of physical design
    including Synthesis, Floor Planning, Power Plan, Integrated Package and
    Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis,
    complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR
    Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC,
    ERC, LVS), DFM and DFY and Tapeout.
  • Expertise in analyzing and converging on crosstalk delay, noise glitch, and
    electrical rules in deepsub micron processes requir...

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