Job Description
Job Description-
We’re hiring an experienced Physical Design (PD) Engineer with 9+ years in ASIC implementation. The role involves delivering high‑performance SoC designs on advanced nodes.
Responsibilities
Own PD flow from floorplan to GDSII
Handle floorplanning, power planning, placement
Drive timing closure and clock optimization
Run CTS, routing, and PPA optimization
Perform signoff: DRC, LVS, IR drop, EM, noise
Collaborate with RTL, STA, DFT, and circuit teams
Debug complex physical/timing issues
Improve PD methodologies
Mentor junior engineers
Required Qualifications
B.E./M.E. in Electrical Engineering or related field
9+ years in ASIC PD
Strong skills in 7nm/5nm/3nm nodes
Expertise in timing closure & integrity analysis
Hands‑on with ICC2/Fusion Compiler, Innovus, PrimeTime
Scripting in Tcl/Perl/Python
Preferred
CPU/GPU/SoC PD experience
Chiplet/multi‑die familiarity
Low‑power design (UPF, power gating)
Tapeout...
We’re hiring an experienced Physical Design (PD) Engineer with 9+ years in ASIC implementation. The role involves delivering high‑performance SoC designs on advanced nodes.
Responsibilities
Own PD flow from floorplan to GDSII
Handle floorplanning, power planning, placement
Drive timing closure and clock optimization
Run CTS, routing, and PPA optimization
Perform signoff: DRC, LVS, IR drop, EM, noise
Collaborate with RTL, STA, DFT, and circuit teams
Debug complex physical/timing issues
Improve PD methodologies
Mentor junior engineers
Required Qualifications
B.E./M.E. in Electrical Engineering or related field
9+ years in ASIC PD
Strong skills in 7nm/5nm/3nm nodes
Expertise in timing closure & integrity analysis
Hands‑on with ICC2/Fusion Compiler, Innovus, PrimeTime
Scripting in Tcl/Perl/Python
Preferred
CPU/GPU/SoC PD experience
Chiplet/multi‑die familiarity
Low‑power design (UPF, power gating)
Tapeout...
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