Job Description
Hi all,
Modernize Chip Solutions is hiring for the below requirements.
Role: Physical Design Engineer
Notice Period: Immediate to 15 days
Location: BLR
Exp: 5+ yrs
Skills Required:
Perform full chip or block-level physical design implementation from Netlist to GDSII
Tools: Cadence Innovus / Synopsys ICC2, PrimeTime / Tempus, Calibre
Strong knowledge of STA, SDC constraints
TCL scripting (Python/Shell)
If Interested, please share your profile to my mail id [email protected]
Modernize Chip Solutions is hiring for the below requirements.
Role: Physical Design Engineer
Notice Period: Immediate to 15 days
Location: BLR
Exp: 5+ yrs
Skills Required:
Perform full chip or block-level physical design implementation from Netlist to GDSII
Tools: Cadence Innovus / Synopsys ICC2, PrimeTime / Tempus, Calibre
Strong knowledge of STA, SDC constraints
TCL scripting (Python/Shell)
If Interested, please share your profile to my mail id [email protected]
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