Physical design engineer (aguascalientes)

Job Detail

Open to relocation to Dallas, TX

Qualifications Mastery of layout and verification tools and methodologies for RF/Analog/Mixed Signal ICs: Mastery in Cadence layout (Virtuoso XL) and Calibre verification (ERC, DRC, LVS) required Able to contribute quickly in a team environment: Strong communication, debugging and analytical skills with complex technical concepts: Experience in DFM hierarchical layout construction for efficient verification and integration Comprehensive understanding of the target process to balance layout and design needs, e.g. cross-talk, RC delay, electro‑migration, IR drop, self‑heating, shielding, matching, guard ring, LOD, WPE and latch‑up. Experience in Analog Layout single digit Fin FET technologies (preferred, but not required) Responsibilities Deliver on project assignments with integrity, commitment, and excellence Efficiently layout sensitive Analog and Mixed Signal circuits conforming to all physical design verification (PDV) requirement...