Job Description
Packaging Design Engineer, Silicon
_corporate_fare_ Google _place_ Mountain View, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
+ 2 years of experience in chip package substrate design using cadence APD (Allegro Package Designer) or mentor expedition.
+ Experience in chip package substrate layout, design rules/verification, DFM and taping out for production.
+ Experience in mobile SOC package design in the following technologies: FCCSP, Package on Package (PoP), InFO, RDL, IPD, 2.5D/3D, Chiplet.
**Preferred qualifications:**
+ Experience in package outline, package routing strategy, bump and Ball Grid Array (BGA) definition and ass...
_corporate_fare_ Google _place_ Mountain View, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
+ 2 years of experience in chip package substrate design using cadence APD (Allegro Package Designer) or mentor expedition.
+ Experience in chip package substrate layout, design rules/verification, DFM and taping out for production.
+ Experience in mobile SOC package design in the following technologies: FCCSP, Package on Package (PoP), InFO, RDL, IPD, 2.5D/3D, Chiplet.
**Preferred qualifications:**
+ Experience in package outline, package routing strategy, bump and Ball Grid Array (BGA) definition and ass...
Ready to Apply?
Take the next step in your AI career. Submit your application to Google today.
Submit Application